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実行可能UMLに基づく組込みシステムネットワーク設計に関する研究<研究成果報告>
https://doi.org/10.24561/00016425
https://doi.org/10.24561/000164259e739204-91f0-4ab4-be7b-03cbd74089d7
名前 / ファイル | ライセンス | アクション |
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KY-AN00095842-42-07.pdf (56.1 kB)
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Item type | 紀要論文 / Departmental Bulletin Paper(1) | |||||
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公開日 | 2014-02-24 | |||||
タイトル | ||||||
タイトル | 実行可能UMLに基づく組込みシステムネットワーク設計に関する研究<研究成果報告> | |||||
言語 | ||||||
言語 | jpn | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | Embedded system network | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | Executable UML | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | System design | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | departmental bulletin paper | |||||
ID登録 | ||||||
ID登録 | 10.24561/00016425 | |||||
ID登録タイプ | JaLC | |||||
タイトル(別言語) | ||||||
その他のタイトル | Research on Embedded Sysem Network Design Based on Executable UML | |||||
著者 |
星野, 達也
× 星野, 達也× 松本, 倫子× 吉田, 紀彦 |
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著者 ローマ字 | ||||||
HOSHINO, Tatsuya | ||||||
著者 ローマ字 | ||||||
MATSUMOTO, Noriko | ||||||
著者 ローマ字 | ||||||
YOSHIDA, Norihiko | ||||||
著者 所属 | ||||||
埼玉大学大学院理工学研究科 | ||||||
著者 所属 | ||||||
埼玉大学大学院理工学研究科 | ||||||
著者 所属 | ||||||
埼玉大学大学院理工学研究科 | ||||||
著者 所属(別言語) | ||||||
Graduate School of Science and Engineering, Saitama University | ||||||
著者 所属(別言語) | ||||||
Graduate School of Science and Engineering, Saitama University | ||||||
著者 所属(別言語) | ||||||
Graduate School of Science and Engineering, Saitama University | ||||||
書誌情報 |
埼玉大学工学部紀要 第一部 論文集 巻 42, p. 36-39, 発行日 2008 |
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年月次 | ||||||
2008 | ||||||
出版者名 | ||||||
出版者 | 埼玉大学工学部 | |||||
出版者名(別言語) | ||||||
出版者 | Faculty of Engineering, Saitama University | |||||
概要 | ||||||
内容記述タイプ | Other | |||||
内容記述 | Embedded systems have recently been working on networks. Such embedded system networks involve communication in various layers, thus their design is more difficult than of single embedded systems. This paper presents how communication exploration can be done in a design process of embedded system networks using an example of event-triggered and time-triggered communication. A design process begins from abstract specification without assuming any communication category, then explores the categories in a stepwise manner, and is followed by physical implementation synthesis. All the models involved in this process are represented in Executable UML. This encourages stepwise decision making, component and framework reuse, and early stage verification. | |||||
版 | ||||||
[出版社版] | ||||||
著者版フラグ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
資源タイプ | ||||||
内容記述タイプ | Other | |||||
内容記述 | text | |||||
フォーマット | ||||||
内容記述タイプ | Other | |||||
内容記述 | application/pdf | |||||
作成日 | ||||||
日付 | 2014-02-24 | |||||
日付タイプ | Created | |||||
アイテムID | ||||||
KY-AN00095842-42-07 |