{"created":"2023-05-15T15:23:35.474081+00:00","id":10466,"links":{},"metadata":{"_buckets":{"deposit":"eb0324d7-7a64-4fcc-9ff4-e003d0b1b577"},"_deposit":{"created_by":15,"id":"10466","owners":[15],"pid":{"revision_id":0,"type":"depid","value":"10466"},"status":"published"},"_oai":{"id":"oai:sucra.repo.nii.ac.jp:00010466","sets":["94:429:431:432:502"]},"author_link":["17750"],"item_113_alternative_title_1":{"attribute_name":"タイトル（別言語）","attribute_value_mlt":[{"subitem_alternative_title":"Chemical flip-chip bonding method using bridge phenomenon between facing electrodes during electroless plating"}]},"item_113_biblio_info_9":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2009","bibliographicIssueDateType":"Issued"}}]},"item_113_date_35":{"attribute_name":"作成日","attribute_value_mlt":[{"subitem_date_issued_datetime":"2009-06-01","subitem_date_issued_type":"Created"}]},"item_113_description_13":{"attribute_name":"形態","attribute_value_mlt":[{"subitem_description":"121p","subitem_description_type":"Other"}]},"item_113_description_23":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"Along with downsizing of metal bumps for flip-chip bonding between chips and substrates, maintaining the interconnection reliability after bonding has been becoming more and more serious especially in case of less than 10 μm-size bumps in recent years. This reliability issue due to the ultra fine pitch bumps is mainly caused by the mechanical process where bumps are deformed by loading under higher temperature ( >250 °C). In addition controlling the mechanical factors such as alignment accuracy, or micro-deformation of bumps, or stress concentration in individual bumps by thermal mismatch has been approaching the fundamental limits. Reductions of bonding temperature and pressure are essential for higher interconnection-density packages. As a candidate of a non-mechanical face-down bonding method under lower temperature, a chemical flip-chip bonding method by electroless plating process has been studied. This method positively utilizes so-called \"bridge\" phenomenon between facing metal pads during electroless Ni-B plating, and enables bump-less interconnect without loading and/or heating at lower temperature (60°C). The interconnect behavior was examined using test chips and substrates with various pad-to-pad configurations. The result confirmed that effective pad width and a ratio of pad pitch to pad width determine the completeness of the interconnection under the condition that distance between facing pads are sufficiently close. The relation between pad-to-pad configurations and interconnect behavior by bridge deposition was also discussed on the basis of the result of the diffusion analysis of the reaction products by finite element method (FEM). A significant potential for finer pitch flip-chip interconnect was experimentally demonstrated using the original test chips and substrates with a minimum pad-pitch of 10 μm.","subitem_description_type":"Abstract"}]},"item_113_description_25":{"attribute_name":"注記","attribute_value_mlt":[{"subitem_description":"指導教員: 埼玉大学大学院理工学研究科連携教授　青柳昌宏","subitem_description_type":"Other"}]},"item_113_description_33":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"subitem_description":"text","subitem_description_type":"Other"}]},"item_113_description_34":{"attribute_name":"フォーマット","attribute_value_mlt":[{"subitem_description":"application/pdf","subitem_description_type":"Other"}]},"item_113_other_language_26":{"attribute_name":"その他の言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_113_record_name_8":{"attribute_name":"書誌","attribute_value_mlt":[{"subitem_record_name":"博士論文(埼玉大学大学院理工学研究科博士後期理工学専攻連携先端研究コース（融合電子技術領域）)"}]},"item_113_text_3":{"attribute_name":"著者 ローマ字","attribute_value_mlt":[{"subitem_text_value":"Yamaji, Yasuhiro"}]},"item_113_text_36":{"attribute_name":"アイテムID","attribute_value_mlt":[{"subitem_text_value":"GD0000062"}]},"item_113_text_4":{"attribute_name":"著者 所属","attribute_value_mlt":[{"subitem_text_value":"埼玉大学大学院理工学研究科博士後期理工学専攻連携先端研究コース（融合電子技術領域）(現: (独)産業技術総合研究所  エレクトロニクス研究部門高密度SIグループ)"}]},"item_113_text_5":{"attribute_name":"著者 所属（別言語）","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Science and Engineering, Saitama University"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"山地, 泰弘","creatorNameLang":"ja"},{"creatorName":"ヤマジ, ヤスヒロ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2018-01-23"}],"displaytype":"detail","filename":"GD0000062.pdf","filesize":[{"value":"10.4 MB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"GD0000062.pdf","url":"https://sucra.repo.nii.ac.jp/record/10466/files/GD0000062.pdf"},"version_id":"a4f40aa5-018c-49ab-bd37-7daff7de72c0"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"thesis","resourceuri":"http://purl.org/coar/resource_type/c_46ec"}]},"item_title":"無電解めっきの導体間ブリッジ析出を応用したフリップチップ接続法に関する研究","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"無電解めっきの導体間ブリッジ析出を応用したフリップチップ接続法に関する研究","subitem_title_language":"ja"}]},"item_type_id":"113","owner":"15","path":["502"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2009-05-29"},"publish_date":"2009-05-29","publish_status":"0","recid":"10466","relation_version_is_last":true,"title":["無電解めっきの導体間ブリッジ析出を応用したフリップチップ接続法に関する研究"],"weko_creator_id":"15","weko_shared_id":-1},"updated":"2023-07-31T07:51:13.157075+00:00"}