@article{oai:sucra.repo.nii.ac.jp:00012580,
 author = {長谷川, 孝明 and 羽渕, 裕真},
 issue = {12},
 journal = {IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences},
 month = {},
 note = {In this paper, a simple frame synchronization method for the SS-CSC system is proposed, and the synchronization performance is analyzed. There have been growing interests in the M-ary/SS communication system and the bi-orthogonal modulation system because these systems can achieve the high frequency utilization efficiency. However, the frame synchronization is difficult. We proposed the SS-CSC system, and evaluated the bit error rate (BER) performance of the SS-CSC system under the completed synchronization. The BER performance of the SSCSC system is much the same as that of the bi-orthogonal modulation system. In this paper, a frame synchronization method using the differential detector and racing counters is proposed. In particular, the lose lock time, the recovery time and the BER performance considering the synchronizing performance are analyzed. In consequence, the BER performance considering the synchronization performance can approach the lower bound of the SS-CSC system by tuning the number of the stages in racing counters., Copyright notice. c1997 IEICE All rights reserved.　 "A Self-Synchronization Method for the SS-CSC System"Hiromasa HABUCHI, Toshio TAKEBAYASHI, Takaaki HASEGAWA. IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, 1997  Vol.E80-A No.12 pp. 2398-2405 許諾No.07RB0055., text, application/pdf},
 title = {A Self-Synchronization Method for the SS-CSC System},
 volume = {80},
 year = {1997},
 yomi = {ハセガワ, タカアキ and ハブチ, ヒロマサ}
}